The present invention relates generally to dynamic random access memory (DRAM) circuits, and, more particularly, to design of DRAM write circuit.
Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor. A simplest DRAM cell comprises a single N-type metal-oxide-semiconductor (NMOS) transistor and a single capacitor. If charges are stored in the capacitor, the cell is said to store a logic HIGH, depending on the convention used. Then if no charge is present, the cell is said to store a logic LOW. Since the charges in the capacitor dissipate over time, DRAM systems require additional refreshing circuitries to periodically refresh the charges stored in the capacitors. Since a capacitor can store only a very limited amount of charges, to fast distinguish the difference between a logic ‘1’ and a logic ‘0’, two bit-lines (BLs) are typically used for each bit with the first in the bit line pair known as a bit line true (BLT) and the other being the bit line complement (BLC). Prior to a sensing, BLT and BLC are equalized to the same voltage. Upon the sensing, the voltages of the BL pair start to split oppositely, e.g., if BLT swings to a higher voltage, then BLC swings to lower voltage. A sense amplifier compares BLT and BLC voltages and outputs either a high or a low voltage to represent a logic value stored in the bit.
The single NMOS transistor's gate is controlled by a word-line (WL). When the WL is asserted a logic high voltage, the single NMOS transistor will be turned on and allow the cell capacitor to be accessed.
In a large DRAM bank, memory cells are organized in blocks, and a bank may contain a plurality of blocks. A WL is coupled to all the cells in a row of a block and a BL pair is coupled to all the cells in a column of the block. Here the row or column is arbitrary, i.e., WLs may run in the column direction and BLs may run in row direction instead. A global bit-line (GBL) pair is coupled to all the BL pairs belonging to the same column of the plurality of blocks through select transistors, which is controlled, conventionally, by a single select signal for the entire bank. The GBL pairs are coupled to the data input/output through multiplexers. When writing or reading the DRAM cells, the select transistors are turned on, so that data can be written into the memory cells from the corresponding GBL pairs and through the corresponding BL pairs, or read from the memory cells through the corresponding BL pairs onto the corresponding GBL pairs. During memory cell refreshing, since the cells are not accessed, so that the select transistors need not be turned on.
In general, accessing a DRAM cell involves WL activation, signal development on the BL pairs, BL sensing, WL deactivation and BL equalization (EQ). BL sensing is a signal write back or refreshing process. When a DRAM cell is being written, outside voltage will charge the storage capacitor, there is no data loss issue. But if the memory cell is not being written and not fully refreshed before connecting its corresponding BL pair to its corresponding GBL pair, data stored in the memory cell may be lost due to large capacitive load of the GBL.
Assuming a 64-bit DRAM has 256 columns in a bank, then each time only ¼ of the BLs need to be accessed. However, because all the select transistors of an entire bank are controlled by a single signal in conventional DRAMs, all 256 BL pairs are connected to their corresponding GBL pairs during a write operation, even though only 64 GBL pairs are forced with outside voltage source. If the memory cells on the rest 192 BL pairs are not fully refreshed prior to the select transistor's turn-on, these memory cells may suffer data loss. For this reason, the write operation in conventional DRAM must be sequential, i.e., writing may only start after a sensing is completed.
FIG. 1 shows a timing sequence of writing in a conventional DRAM. Prior to the writing 108, the BLs are equalized in time slot 102. At the beginning of the writing, the WL starts to develop in time slot 104, and maintains activated throughout the entire write cycle 100. Sensing occurs in time slot 106. During this time, all the cells coupled to the activated WL are refreshed to their full capacity. Writing to the selected cells happens in time slot 108 after the sensing period 106 is completed. Due to these sequential executions, the writing cycle 100 is particularly long, which limits the overall speed of the DRAM.
One way to overcome this limitation is to selectively turn on only those select transistors for the BL pairs being accessed, while keep the rest of the select transistors in the memory bank in off state. But this requires additional select signal lines, which will increase the memory die size.
As such, what is desired is a DRAM writing scheme that allows early writing, i.e., simultaneous writing and sensing or even writing ahead of sensing, without increasing memory die size.